1. Field of the Invention
The present invention relates to a television(TV) which receives a broadcasting signal having caption data, and more particularly, to a data slicer which detects caption data.
2. Background of the Related Art
A caption television (TV) is generally adapted to display a composite video blanking signal (CVBS), or a composite video signal, from a broadcasting station through a sequence of signal processes, wherein the CVBS includes additional information or character information for hearing impaired people, which is in synchronization with an audio signal.
In the caption TV, caption data is placed on an odd or even field line 21 in a vertical blanking interval (VBI) of the CVBS, referred to hereinafter as xe2x80x9cNTSC VBI line 21xe2x80x9d.
With reference to FIG. 1, the NTSC VBI line 21 generally has a signal characteristic composed of a horizontal synchronization part, color burster, 7-cycle sinusoidal wave, 001-bit start bit and 2-bite caption data, wherein first and second characters of the 2-bite caption data are generally composed of 7-bit pure data and 1-bit parity bit, respectively.
The NTSC VBI line 21 may be transmitted via a video tape, TV air waves or cable. However, the NTSC VBI line 21 is subjected to considerable distortion due to a tension relaxation and temperature variation of the video tape resulting from frequent copies and various noises on channels of the TV air waves and cable. Such distortion results in a glitch or phase error on the NTSC VBI line 21.
A data slicer is the kernel in determining the performance of a caption decoder (for example, an NTSC closed caption decoder), because it can detect desired caption data from the distorted NTSC VBI line 21.
There is shown in block form the construction of an example of a conventional data slicer. A 7-cycle sinusoidal wave on the NTSC VBI line 21 is used for the frequency/phase locking of a phase locked loop (PLL) so that the caption data on the NTSC VBI line 21 can be detected by a separate synchronization signal locked to a frequency of 503 KHz.
In another example of a conventional data slicer, the 7-cycle sinusoidal wave on the NTSC VBI line 21 is used as a sample/hold interval for the detection of a reference voltage for the high/low determination. In this data slicer, values of over-sampled data regions are compared with the reference voltage and the caption data on the NTSC VBI line 21 is detected on the basis of the number of 1s and 0s as a result of the comparison. However, the conventional data slicers have the following problems.
Firstly, in the data slicer where the 7-cycle sinusoidal wave on the NTSC VBI line 21 is used for the frequency/phase locking, a separate PLL is required only for a sampling of the NTSC VBI line 21, resulting in an increase in the size of hardware (H/W). Further, because the locking is effected for a short period of seven cycles, the PLL must have a relatively high performance, thereby increasing the cost of H/W. Moreover, in the case where the 7-cycle sinusoidal wave itself is subjected to deterioration, a faulty operation occurs in the data slicer.
Secondly, in the data slicer where the 7-cycle sinusoidal wave on the NTSC VBI line 21 is used as the sample/hold interval for the detection of the reference voltage for the high/low determination, 1/0 counting and comparing operations are performed, resulting in a degradation in noise coping capability. As a result, the data slicer may mis-recognize a waveform distorted in an analogous form to an NTSC caption signal as the NTSC caption signal, thereby causing a faulty operation.
Accordingly, the present invention is directed to a data slicer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a data slicer which detects 7-cycle sinusoidal wave, a start bit and actual caption data in a successive high/low detection manner, so that a faulty operation due to noises can be prevented from occurring, resulting in an increase in the reliability of data detection.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, a data slicer includes an analog to digital converter for sampling an input analog signal to convert it into a digital signal, a caption signal reader for determining upper/lower levels which are reference levels from the digital signal and detecting a signal of the line in which a caption data is inserted by applying a successive high/low detection manner to each of compared result between the digital signal and upper/lower level signals, a comparator for respectively comparing the digital signal with the upper/lower level signals and outputting the compared results to the caption signal reader, a data reader for outputting actual caption data by applying the successive high/low detection manner to the output of the comparator when a line signal in which the caption data is inserted is detected by the caption signal reader, and a controller for controlling the detection of the line signal in which the caption data is inserted, and a reading of the actual caption data.
The caption signal reader includes a reference level determination unit for detecting high/low peaks of the digital signals respectively and determining upper/lower levels which are reference levels by giving an offset to a difference of the two peak signals, a sinusoidal wave detector for storing and shifting the results of the comparator respectively, and for detecting a certain interval of an inherent 7-cycle sinusoidal wave of a caption signal in a successive high/low detection manner, and a start bit detector for storing and shifting the compared results of the comparator respectively, and for detecting a start bit inserted after the 7-cycle sinusoidal wave of the caption signal in a successive high/low detection manner, when the sinusoidal wave detector outputs a sinusoidal wave detection signal.
The reference level determination unit includes a high peak calculator for detecting a high peak of the digital signal, a low peak calculator for detecting a low peak of the digital signal, a difference calculator for calculating a difference between output values of the high and low peak calculators, a divider for outputting an offset value by dividing the resulted value from the difference calculator by a certain value, a mean value calculator for obtaining a mean value between the output values from the high and low peak calculators, and a level output unit for obtaining and outputting an upper-level by adding the offset value of the divider to the output value of the mean value calculator and a lower level by subtracting the offset value of the divider from the output value of the mean value calculator.
The sinusoidal wave detector includes a first shift register divided into several parts, for storing and shifting the result of comparison UHL between the digital signal and the upper level of the reference level determination unit, a second shift register divided into several parts, for storing and shifting the result of comparison LHL between the digital signal and the lower level of the reference level determination unit, a successive low discriminator for discriminating whether values of the divided parts of the first shift register are all in a low state, a successive high discriminator for discriminating whether values of the divided parts of the second shift register are all in a high state, a data determination unit for determining 1 or 0 utilizing the discriminated results of the successive low and high discriminators when a determination enable signal is input from the controller, a first register for storing an output value from the data determination unit, and a run-in signal output unit for outputting a run-in signal if the value stored in the first register is a part of the 7-cycle sinusoidal wave.
Each of the first and second shift registers is designed to have a size capable of storing digital data for a period of 1.5 cycle, and is divided into three regions.
Each divided region of the first and second shift registers sets specific regions having certain margins at its start and end points, so that the successive low and high discriminators discriminate successive low/high only for the data stored in the specific region.
The start bit detector includes a first shift register for storing and shifting the result of comparison UHL between the digital signal and the upper level of the reference level determination unit, having specific regions with certain margins at start and end points, a second shift register for storing and shifting the result of comparison LHL between the digital signal and the lower level of the reference level determination unit, having specific regions with certain margins at start and end points, a successive low discriminator for discriminating whether values of the specific regions of the first shift register are all in a low state, a successive high discriminator for discriminating whether values of the specific regions of the second shift register are all in a high state, a data determination unit for determining 1 or 0 utilizing the discriminated results of the successive low and high discriminators when a run-in signal is output from the sinusoidal wave detector, a first register for storing the output of the data determination unit, and a start bit output unit for outputting a start bit signal when the value stored in the first register is indicative of a start.
The data reader includes a first shift register for storing and shifting the result of comparison UHL between the digital signal and the upper level of the reference level determination unit, having specific regions with certain margins at start and end points, a second shift register for storing and shifting the result of comparison LHL between the digital signal and the lower level of the reference level determination unit, having specific regions with certain margins at start and end points, a successive low discriminator for discriminating whether values of the specific regions of the first shift register are all in a low state, a successive high discriminator for discriminating whether values of the specific regions of the second shift register are all in a high state, a data determination unit for determining 1 or 0 by the discriminated results of the successive low and high discriminators when a run-in signal and a start bit are output from the sinusoidal wave detector and the start bit detector, respectively, a second register for storing an output from the data determination unit, and a caption data output unit for reading an actual caption data stored in the second register by an output flag signal of the controller and externally outputting it.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.